In substation automation it is essential to reach highest possible reliability and availability, which is a challenge for every designer of such installations. Several contradictory aspects need to be implemented in the same design, as, among others, I/O circuits need to be galvanic insulated for elimination of ground loops or double insulation needs to be implemented. While high reliability and high availability are desired, the respective I/O circuits need to be protected against EMC, which leads to an increase in the amount of needed components. While the designer decides, where the galvanic isolation takes place in such installations, usually the galvanic isolation is implemented between external interface and internal electronics. Product safety standard IEC 60255-27 defines categories for interfaces in several circuit classes such as HLV, PELV etc., thus resulting in various possible combinations for decoupling between classes such as HLV to PELV, PELV to PELV, HLV to HLV etc.
For example, for HLV to PELV with IEC 60255-27 as product standard, a rated insulation voltage of 300V AC/DC, reinforced insulation, overvoltage category III and pollution degree II, and electro static discharge (ESD) according to IEC 60255-26; IEC 61000-4-2; IEEE Std C37.90.3 with an air discharge of 15 kV and contact discharge of 8 KV, required clearance and creepage distances for galvanic isolations are designed to withstand surge and high voltage AC/DC tests according to required overvoltage category. In general, the rated impulse voltage (RIMV) is smaller than the air discharge voltage to be applied for ESD (RIMV 4 kV≤ESDair=15 kV). Classical thumb of rule for clearance distances is 1 kV/mm with required ESD clearance 15 mm i.e. according to IEC 60255-27 5.5 mm (reinforced).
However, it is obvious that the specified clearance and creepage distances according to IEC 60255-27 cannot withstand high voltage transient such as ESD pulses and flash-over may occur. Due to the injected transients a current flows through the galvanic isolation, occurred by a charge respectively discharge current of coupling capacity. This current causes often interferences with electronics on the secondary as well as on primary side of such galvanic isolation apparatus, for example of an isolation transformer. The measures know from prior art to avoid said transients such as, for example, adding protection circuits to limit maximum over voltage and/or to limit maximum current flowing into electronics or adding coating or potting, in a disadvantageous manner increase the required space and increase manufacturing and thus device costs.
US 2014/048322 A1 describes an electronic apparatus comprising a circuit board, an insulation structure and a transformer. The circuit board has a top surface, a bottom surface and an opening extending across the top surface and the bottom surface.
U.S. Pat. No. 6,563,056 B1 describes a printed circuit board (PCB) assembly which comprises at least two separate PCB sections, whereby an insulation transformer is used as a support structure to mechanically interconnect the sections.
DE 10 2013 113861 A describes a galvanic separating device which is simple to produce as a planar transformer and simple to equip and which can be soldered onto a circuit board together with other components on the circuit board.